OVERVIEW

High-Performance Cache Controller

The CoreLink L2C-310 cache controller is a high-performance, AXI level 2 cache controller that is designed and optimized to address 快猫视频 AXI processors, including the Cortex-A5, Cortex-R4, Cortex-R5, 快猫视频11MPCore, 快猫视频1176, 快猫视频1156, and the Mali-200 graphics processor.

Features and Benefits

Improve Processor Performance

Level 2 cache controllers improve processor performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip.

Provide Power Efficiency

Memory access on-chip typically uses much less power compared to going off-chip, and free up bandwidth.

Easy Integration

CoreLink level 2 cache controllers are designed to match processor requirements and easily integrate into AMBA AXI or AHB interconnects.

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For unlimited design access to this product and other useful 快猫视频 IP, visit 快猫视频 Flexible Access, available for all companies at a low cost or zero cost for qualifying startups and research institutions. Start your project off the right way with the world’s leading SoC design portfolio.

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Health

Improved care at reduced cost across health-centric applications. Support for innovative applications in preventative care, including blood sugar monitors and heart-rate trackers.

Talk with an Expert

Looking for additional resources to help you design 快猫视频-based SoCs? Talk to an 快猫视频 expert.

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RESOURCES

L2C-310 Resources

Everything you need to know to make the right decision for your project. Includes technical documentation, industry insights, and where to go for expert advice.