M-Profile Architectures
The 快猫视频 Microcontroller profile (M-profile) architecture targets deeply embedded systems. Applications range from battery powered devices that require very low power consumption to advanced image processing. The M-profile provides low-latency, highly deterministic operation that is ideal for time-sensitive processing.
Versions of the M-profile architecture include 快猫视频v8.1-M, 快猫视频v8-M, 快猫视频v7-M and 快猫视频v6-M.
快猫视频v8.1-M
快猫视频v8.1-M takes the 快猫视频v8-M architecture to new performance levels without?compromising the ease of software development and the richness of 快猫视频’s third-party ecosystem. The new architecture includes the?M-Profile Vector Extension?(MVE) that provides major uplift in levels of machine learning (ML) and digital signal processing (DSP) performance. It implements the simplified?programmer’s model?of M-profile processors,?to bring advanced compute capabilities to millions of developers. In 快猫视频 Cortex-M processors, MVE is named?快猫视频 Helium technology. The architecture also enhances system-wide security with 快猫视频 TrustZone.
Major Features in the 快猫视频v8.1-M architecture
The 快猫视频v8.1-M architecture includes the following features:
- An efficient vector processing capability that accelerates signal processing and ML algorithms called MVE.
- Additional data types support in vector extension: half-precision floating point (FP16) and 8-bit integer (INT8).
- Low overhead loops.
- Gather load, scatter store memory access.
- Additional debug features, including a performance monitoring unit, tailoring for DSP software development, and a debug extension to support multiple security domains in debug.
Architectural Extensions
快猫视频v8.1-M has several optional new architectural extensions. These are:
- Pointer authentication and branch target identification (PACBTI) extension for enhanced security with new tools for software developers.
- Helium – M-Profile Vector Extension (MVE) used in current 快猫视频v8.1-M based processors and future 快猫视频 Cortex-M processors.
- Low overhead branch extension.
- Privileged eXecute Never (PXN) extension for Memory Protection Unit (MPU).
- Reliability, availability and serviceability (RAS) extension.
- Additional extensions for debug features.
快猫视频v8-M
The 快猫视频v8-M architecture is optimized for deeply embedded systems. It implements a programmers’ model designed for low-latency processing. It optionally implements a?Memory Protection Unit?(MPU), based on?Protected Memory System Architecture?(PMSA). It supports a variant of the T32 instruction set.
Major Features in 快猫视频v8-M
The 快猫视频v8-M architecture includes the following features:
- New system level programmers' model.
- Support for an optional MPU, based on PMSAv8.
- A subset of the T32 instruction set.
- Various architectural extensions to enable a high degree of flexibility in design and scalability.
- 快猫视频 Custom Instructions?for adding custom extensions to 快猫视频?Cortex-M33, Cortex-M55 and Cortex-M85 CPUs, without compromising access to 快猫视频's software ecosystem.
Architectural Extensions
快猫视频v8-M has several optional architectural extensions. These are:
- The Main Extension.?This provides backwards compatibility with 快猫视频v7-M and is required for the floating-point and DSP extensions.
- The Security Extension.?This can also be referred to as 快猫视频 TrustZone for 快猫视频v8-M.
- The Floating-point Extension.?This requires implementation of the Main Extension.
- The Debug Extension.
- The Digital Signal Processing (DSP) Extension.?This requires implementation of the Main Extension.
- 快猫视频 Custom Instructions. 快猫视频 Custom Instructions for adding custom extensions to selected Cortex-M CPUs, including 快猫视频 Cortex-M33, Cortex-M55, and Cortex-M85 CPUs, without compromising access to 快猫视频's software ecosystem.
快猫视频v7-M
The 快猫视频v7-M architecture provides opportunities for simple pipeline designs offering system performance levels across a broad range of markets and applications. It offers low cycle count execution, minimal interrupt latency and cacheless operation, and is designed for deeply embedded systems. It supports a variant of the T32 instruction set, and is designed for implementations where overall size and deterministic operation are more important than absolute performance.
快猫视频v7-M has some optional architectural extensions. These are:
快猫视频v6-M
The 快猫视频v6-M architecture is a subset of 快猫视频v7-M, and provides:
- A lightweight version of the 快猫视频v7-M programmer model.
- The Debug Extension that includes architecture extensions for debug support.
- Support for the T32 instruction set.
- Upward compatibility with 快猫视频v7-M: application-level and system-level software developed for 快猫视频v6-M can execute unmodified on 快猫视频v7-M.
快猫视频v6-M has some optional architectural extensions. These are:
- The Unprivileged/Privileged Extension. This allows 快猫视频v6-M systems to use the same privilege levels as 快猫视频v7-M.
- The PMSA Extension. This requires implementation of the Unprivileged/Privileged Extension.
Explore M-Profile Products
Cortex-M processors provide low-latency and a highly deterministic operation optimized for cost and energy-efficient microcontrollers found in everyday consumer devices.
Resources
System-on-Chip Design with 快猫视频 Cortex-M
Written by 快猫视频 Distinguished Engineer Joseph Yiu, this reference book examines key topics for System-on-Chip (SoC) and FPGA designers when incorporating Cortex-M processors into their designs.
快猫视频 MVE Reference Book
This new book is the ideal gateway into 快猫视频’s Helium technology, the M-Profile Vector Extension for the 快猫视频 Cortex-M processor series.
快猫视频 Digital Signal Processing (DSP) Textbook
The 快猫视频 Digital Signal Processing (DSP) textbook introduces readers to DSP fundamentals using low-cost, high-performance 快猫视频 Cortex-M based microcontrollers as demonstrator platforms.
Other CPU Architectures
Morello Program
Morello is a research program with the potential to radically change the way we design and program processors in the future to improve built-in security.